Patent Portfolio on Chip Design For Smart Memories

This portfolio is related to:

  • Design on memory, focusing on low power consumption as well as offering area saving integrated circuit design solutions;
  • FDSOI design for core circuits.

 

Targets:

  • Target devices: DRAM, eDRAM, FPGA, Flash, FBC, SRAM,…
  • Target markets: stand-alone memory, embedded memory, consumer logic.

 

Patent Portfolio Proposed

  • Portfolio comprising 34 patent families corresponding to 188 current patent applications filed between 2009 - 2014, with majority of filings in 2010-2011;
  • 157 granted (83,5 %) -->  strong advantage !
  • 31 published and pending (16,5 %)

 

Geographical coverage :

USA / France / South Korea / China / Germany / Taiwan / Great Britain / Singapore / Japan.

 

Main Value Proposition

  • Lower Cost of Ownership;
  • Efficient Design Architecture: denser block organization / smaller circuit blocks / integration of new circuits for yield enhancement;
  • Lower Power Consumption: Reduction of static and dynamic power consumption. 

 

Memory benefits on peripheral circuits:

  • Area reduction: Less sensitivity to variability & Innovative and denser design techniques
  • Performance increase: Higher efficiency / Circuit simplification (less stages to propagate through, less noise generation) / Lower Impedance
  • Power reduction: Power reduced by back gate control and smaller transistor count  this is a very powerful tool! / Size reduction of periphery circuits and in particular of the refresh circuits smaller devices
Technologies: 
Transactions: 

Company details

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